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Graded doping profile in the channel of vertical sub-100nm nMOSFETs was
investigated in this study. Conventional single step ion implantation was used to form
the asymmetric graded doping profile in the channel. No large-angle-tilt implant is
needed. The device processing is compatible with conventional CMOS technology. In a
graded-channel-doping device, with the higher doping near the source, drain induced
barrier lowering and the off-state leakage current are reduced significantly. The graded
doped channel also has a lower longitudinal electric field near the drain. Therefore, hotcarrier
related reliability is improved substantially with this type of device structure.
By: X. Chen, Q. Ouyang, Geng Wang, S. Banerjee
Published in: IEEE Transactions on Electron Devices, volume 49, (no 11), pages 1962-8 in 2002
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