Circuit Implementation of a dc-balanced 8B10B-P Transmission Code with Local Parity

This report describes a hardware implementation using combinational logic for the encoding and decoding circuits and the validity check of the dc-Balanced 8B10B-P Transmission Code with Local Parity described in US Patent 5,699,062. Less than 300 primitive logic gates are required in each direction arranged in logic paths at most seven deep. The circuits have been structured so pipe-lining can be used with modest overhead to reduce the logic depth to 6, 5, 4, or even 3 per stage.

By: Albert X. Widmer

Published in: RC23924 in 2006


This Research Report is available. This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. It has been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g., payment of royalties). I have read and understand this notice and am a member of the scientific community outside or inside of IBM seeking a single copy only.


Questions about this service can be mailed to .