This report describes a hardware implementation using combinational logic for the encoding and decoding circuits and the validity check of the dc-Balanced 8B10B-P Transmission Code with Local Parity described in US Patent 5,699,062. Less than 300 primitive logic gates are required in each direction arranged in logic paths at most seven deep. The circuits have been structured so pipe-lining can be used with modest overhead to reduce the logic depth to 6, 5, 4, or even 3 per stage.
By: Albert X. Widmer
Published in: RC23924 in 2006
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