The continued scaling of complementary metal oxide semiconductor (CMOS) device technologies has lead to continued device shrinkage and decreases in the Vdd, the operating voltage of the device transistors. Scaling has meant denser circuitry overall, thinner silicon (e.g., SOI) in logic applications and less charge on capacitors for volatile memory. These trends have resulted in devices being more sensitive to soft errors since now low energy alpha particles can flip a memory bit or alter timing in a logic circuit. The alpha particle source is, in many cases, self inflicted, because alpha particles are commonly generated in materials adjacent to the chip, solders and in the packaging. In this paper we discuss several schemes by which these alpha particles can be blocked, such that all of their energy is absorbed before reaching the sensitive silicon circuitry at the transistor level. These alpha blocking layers are shown to be effective both through the use of modeling and through experimental measurements.
By: C. Cabral Jr; K. P. Rodbell; M. S. Gordon
Published in: RC24016 in 2006
LIMITED DISTRIBUTION NOTICE:
This Research Report is available. This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. It has been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g., payment of royalties). I have read and understand this notice and am a member of the scientific community outside or inside of IBM seeking a single copy only.
Questions about this service can be mailed to reports@us.ibm.com .