On the Applicability of Compressive Sampling in Fine Grained Processor Performance Monitoring

Efficient gathering of micro-architectural performance information generated at a processor core is required for real-time performance analysis. Performance information can be expected to be highly structured allowing it to be compressed, but the computational burden of conventional compression techniques exclude their use in this environment. We consider the use of new mathematical techniques that allow a signal to be compressed and recovered from a relatively small number of samples. These techniques, collectively termed Compressive Sampling, are asymmetric in that the compression is simple, but the recovery is complex. This makes them appropriate for applications in which the simplicity of the sensor can be offset against complexity at the ultimate recipient of the sensed information. We evaluate the practicality of using such techniques in the transfer of signals representing one or more micro-architectural counters from a processor core. We show that compressive sampling is usable to recover such performance signals, evaluating the trade-off between efficiency, accuracy and practicability with its various variants. We identify deficiencies in the existing techniques and propose refinements which may be used to enhance the use of compressive sampling for processor performance monitoring.