NOTE: FIGURES NOT INCLUDED IN PS FILE. Full paper with figures published in IBM Journal of Research and Development, v. 39, n. 5, p. 547-567, September, 1995. Long, on-chip interconnections with dimensions larger than the minimum groundrules are rigorously analyzed and experimentally characterized for the first time. A test vehicle has been built and characterized with representative wiring found in high-performance CMOS microprocessor chips, namely line lengths of 0.8 - 1.6 cm, and line widths of 0.9 - 4.8 &mu.m using 5-metal-layers structure. The need for distributed RLC transmission-line representation is highlighted through measured and simulated results. By showing the problems encountered when using long, non-uniform on-chip transmission lines, guidelines are developed to take advantage of the lower resistance interconnects for use in high-speed, cycle-determining paths. Such guidelines are given both for present day and optimized wiring practices and cross sectional structures.
IBM Journal of Research and Development, v. 39, n. 5, p. 547-567, September, 1995.
By: A. Deutsch, G. V. Kopcsay, C. W. Surovic, B. J. Rubin, L. M. Terman, R. P. Dunne and T. Gallo
Published in: RC20068 in 1995
LIMITED DISTRIBUTION NOTICE:
This Research Report is available. This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. It has been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g., payment of royalties). I have read and understand this notice and am a member of the scientific community outside or inside of IBM seeking a single copy only.
Questions about this service can be mailed to reports@us.ibm.com .