Extension of an InfiniBand Host Channel Adapter Model and Performance Analysis

The requirements for I/O hardware components become increasingly demanding both in performance and in functionality leading to highly complex implementations, difficult to test and to upgrade. In this paper we use a C-written model of an InfiniBand Host Channel Adapter and use it to evaluate both the use of a high level language to model a complex ASIC design and the actual design. With the model we are able to illustrate the strengths and identify the bottlenecks of our architectural choices leading to early architectural changes and a more performant hardware design.