Cache Injection for Private Cache Architectures (Concept Paper)

The memory wall is considered to be one of the biggest challenges for multi- and many-core architectures. Putting more and more cores on the processor die considerably increases the required memory bandwidth far in excess of the available memory subsystem bandwidth. The major bottleneck for achievable memory bandwidth are limited offchip bandwidth and coherence requirements. Larger caches and deeper cache hierarchies can alleviate the memory bandwidth problem only to some extent. For I/O-related operations, cache injection has the potential of mitigating the pressure on the memory subsystem by reducing the number of necessary memory transfers. However, the mechanisms proposed so far are mainly aimed at non-virtualized environments. In this paper we propose concepts for cache injection in systems using private cache architectures with special focus on providing support for heavily virtualized devices. Therefore we study different aspects of cache injection, i.e., the device-processor interaction, the injection process in the cache-coherent processor fabric, as well as the cache itself. The key characteristics of our proposed methods are better directivity, less overhead on the processor interconnect, and better control mechanisms for cache injection.

By: F. Auernhammer, P. Sagmeister

Published in: RZ3776 in 2010


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