We present a brief review of some of the most promising ideas in power-aware design at
the (micro)architecture level. This review is based primarily on the most recently published work
in relevant architecture and design conferences or workshops. We also refer to prior fundamental
work on analytical models of pipelined and parallel machine performance and recast the results
to fit the modern framework of joint power-performance metrics. The second part of the paper is
an attempt at comparing the power-performance scalability of selected microarchitecture
paradigms of interest: e.g. wide-issue out-of-order super scalar, multi-cluster superscalars, SMT
and CMP. In conclusion, we touch on future areas of research on the topic of power-aware architectures.
By: Pradip Bose
Published in: RC22234 in 2001
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