Simulation Study of a Metal-gate / High-k Gate Stack for Low-Power Applications

Conventional polysilicon gates (PG) suffer from carrier depletion which limits the effective scaling of the gate insulator stack. As a result, metal gates (MG) are currently of great interest as a means to continue device scaling through reduced effective gate insulator thickness [1-6]. Their competitiveness relative to PG, however, depends strongly on the MG work function as well as the off-state leakage target (Isoff) of the application desired [7,8]. If a near-midgap gate is used for a highperformance application, the required reduction in channel doping to attain the same Isoff leads to a buried channel device due to the weak confining field at the surface [7-9]. On the other hand, the intrinsically high Vt of near-midgap gates makes them well-suited for low-power applications [8]. Fig. 1 illustrates this basic concept by showing how a low-power application (Isoff =300 pA/µm) with nearmidgap MG requires channel doping comparable to that of a high-performance one (Isoff =300 nA/µm) with PG, thereby restoring the confinement needed to avoid a buried-channel device.

The purpose of this work is to study the competitiveness of a near-midgap metal/high-κ gate stack for a low-power application using mixed-mode simulations of inverter delay chains. We address key design issues including (1) choice of gate stack based on leakage requirements; (2) matching of rolloff characteristics between PG and MG; (3) effect of potential mobility degradation due the high-κ gate stack; and (4) junction leakage for ultralow power requirements.