Creating the BlueGene/L supercomputer from low power System-on-a-Chip ASICs

Traditional supercomputer design, using large powerful networks coupled to state-of-the-art processors, is hitting power and cost limits. The major drivers for cost are increased system complexity and stringent power requirements. Current directions in integration, power, and technology are driving toward using multiple modest cores on a single chip rather than one high-performance processor. This is especially significant as W/FLOPS ratio will not significantly improve with future technologies. These considerations motivated the pursuit of BlueGene/L as a massively parallel system design, based on embedded PowerPC processors with a relatively modest clock rate. By adopting a cost-effective SoC approach, a low-cost design with low power consumption is realized, allowing for aggressive system integration.

By: Arthur A. Bright, Matthew R. Ellavsky, Alan Gara, Ruud A. Haring, Gerard V. Kopcsay, Robert F. Lembach, James A. Marcella, Martin Ohmacht, Valentina Salapura

Published in: Proceedings of 2005 IEEE International Solid-State Circuits Conference, Piscataway, NJ, , IEEE. , vol.1, p.188-9 in 2005

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