8B/10B Encoding and Decoding for High Speed Applications

The 8B/10B Encoder and Decoder circuit designs presented here attempt to deliver the best possible speed and exploit the characteristics of the standard cell library for the IBM CMOS-7S or similar technology (Ref. 4) to the fullest. An implementation with both a single CoDec circuit and for parallel circuits is shown.

By: Albert X. Widmer

Published in: RC23408 in 2004


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