Accurate De-Embedding of CMOS Transistors from On-Wafer Measurements up to 110 GHz using Automatically Characterized CMOS Calibration Structures

This paper presents a de-embedding sequence for CMOS transistors that is very accurate from DC to frequencies above 110 GHz. In a first step, a combination of on-wafer TRL and LRM calibrations defines a 50 reference plane at a distance of less than 10m away from the device under test (DUT). The calibration method is based on a compact set of on-wafer structures consisting of a thru connection (thru), a nominal short (reflect), a moderate length transmission line (line), and a nominal load (load). The equivalent electrical values of the above structures are automatically determined with high precision during the calibration process and have therefore not to be known prior to the calibration. This allows the method to be applied (but not limited) to CMOS processes tolerating their relatively large process variations and parasitics. It also makes additional off-wafer calibration kits dispensable. In a second iteration step, a de-embedding sequence that relies on the measured Y- and Z-parameters of an open- and a short-circuit is used to take the parasitic influence of the last few micrometers of wire connection between the reference plane and the transistor into account. The described method is utilized for the de-embedding of CMOS test transistors up to a frequency of 110 GHz. The transistors are manufactured on IBM’s 0.11 um Cu11 line and have a transit frequency in excess of 80 GHz, making advanced de-embedding techniques a necessity for the determination of the equivalent circuit elements including the internal noise sources.