Final Report for Contract N6601-99-C-6000

We report work on problems related to the fabrication of a SiGe pMODFET static
divider circuit on sappahire. We have fabricated SiGe pMODFET devices on silicon-on-sapphire with transconductances as high as 377 mS/mm, fT = 50 GHz and fmax = 114 GHz. We have found that the device characteristics depend very sensitively on the epitaxial layer structure. Very small changes in the layer thickness or doping
concentration result in a lower fT and/or a shift in Vt that can significantly reduce the
maximum operating frequency of this circuit. To obtain sufficient device yield to achieve
working circuits, choices were made in the fabrication processes that also reduced the
operating frequency range of the circuits. Specifically, Lg was chosen to be 0.15 m and
the dielectric layer between M1 and M2 was relatively thin. Devices with a shorter gate
length would have a higher ft and a thicker dielectric layer would reduce the parasitic
capacitances. The circuit we fabricated on bulk Si operated up to 3 GHz, with devices
having fT = 17 GHz and Vt = 0.18 V. Circuit modeling indicates that the maximum
operating frequency for this circuit fabricated on a thin SiGe-on-sapphire wafer with
devices having fT = 55-72 GHz and an optimized threshold voltage of ~0.3 V would be
25-35 GHz. Early on we found that the quality of available epitaxial SOS wafers was not good enough for circuit fabrication. Our collaborators at the University of Wisconsin, Madison (UW) have shown that bonded SOS wafers are very promising from a defect perspective. pMODFET layer structures grown on bonded SOS wafers have hole mobility comparable to that on bulk Si. The fact that bonded SOS wafers are stable only up to temperatures of ~600 o C would not have been a problem for this project, since all fabrication steps are executed at much lower temperatures. Unfortunately, the bonded SOS wafers from UW arrived too late to be used for our final device fabrication run. In any case, to take full advantage of the sapphire substrate, thin SiGe-on-sapphire wafers are required. A similar process can be used for bonding SiGe to sapphire, using thick strain-relaxed step-graded SiGe buffer layers grown epitaxially on SOI as the source of SiGe. However, additional work is necessary to develop a good method to controllably thin the transferred SiGe buffer layer.