A major consumer of microprocessor power is the issue queue. Several microprocessors, including the Alpha 21264 and POWER4TM, use a compacting latch-based issue queue design which has the advantage of simplicity of design and verification. The disadvantage of this structure, however, is its high power dissipation. In this paper, we explore different issue queue power optimization techniques that vay not only in their performance and power char-acteristics, but in how much they deviate from the baseline implementation. By developing and comparing techniques that build incrementally on the baseline design, as well as those that achieve higher power savings through a more significant redesign effort, we quantify the extra benefit the higher design cost techniques provide over the more straightforward techniques.
By: Alper Buyuktosunoglu, David Albonesi, Pradip Bose, Peter W. Cook, Stanley E. Schuster
Published in: RC22380 in 2002
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