Compact Hardware Architecture for 128-bit Block Cipher Camellia

A compact hardware architecture for the Feistel-type cipher Camellia is proposed, and its performance is compared with the SPN-type cipher AES. In our architecture, a 64-bit F function is halved, and the other functions are also halved, shared, and merged together. A high-speed architecture as well as a compact version was implemented using 0.13-mm and 0.18-mm CMOS ASIC libraries and FPGA. A smallest size of 6.26 Kgates with 202 Mbps and a highest throughput of 2.15 Gbps with 29.8 Kgates were obtained from the ASICs. On the same FPGA platform, the performance of our compact and high-speed architectures is 2 times higher than conventional implementations. Even compared with high-performance AES hardware using the same ASIC libraries and FPGA, the performance of our Camellia is equivalent in both speed and size for compact implementation.