Predicting Interconnect Requirements in Ultra-Large-Scale Integrated Control Logic Circuitry

Information about interconnect requirements is needed for the successful design of today’s complex, ultra-large-scale integrated (ULSI) chip circuitry. Estimates of interconnect requirements, including average wire-length and wire-length distributions in chip designs, are obtained by evaluating existing on-chip wire-length distribution models. The overall objective of this paper is to present estimates and measurements of interconnect requirements in ULSI control logic circuitry. One goal of this paper is to present a comprehensive assessment of existing models and to quantify the agreement observed (1) between estimates and measurements of average wire-length in individual designs in real chips, and (2) between wire-length distributions provided by the models and wire-length distributions obtained from measurements. Another goal of this paper is to present an assessment of the interconnect requirements for all of the control logic in a chip. For this study, actual interconnect data is measured in ASIC-like control logic designs in the six functional units of the 1.3GHz POWER4. This paper compares interconnect measurements with estimates for control logic in individual designs, in functional units, and in the entire POWER4 core. The results presented in this paper show that the estimates are typically lower than the actual wire-length measurements. The results also show that the estimates of the total wire-length for all of the control logic in the POWER4 agree to within 31% of the total measured wire-length.

By: Mary Yvonne Lanzerotti; Giovanni Fiorenza; Rick A. Rand

Published in: RC23500 in 2005


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