Reliability and Integration of Ultra-Thin Gate Dielectrics for Advanced CMOS

        The rapid scaling of CMOS technology over the last few years has resulted in the reduction of gate dielectric thickness to only a few nanometers. Some estimates suggest that standard SiO2 (or its nitrogen containing variants) will cease to be useful when the thickness is reduced to between 1.0-2.0 nm. The major causes for concern, assuming that such thin dielectrics may be grown with an acceptable yield, seem to be centered upon either process integration issues, (for example boron penetration), or upon the increasing gate leakage which lead to questions regarding dielectric integrity and reliability, or to standby power consumption. The future of CMOS down to and below the 0.1 m gate lengths may well hinge on finding a replacement of silicon dioxide as the gate insulator. However, even for 2.0-4.0 nm dielectrics currently being used for the development of 0.1-0.25 m technologies. There is only limited understanding of the issues pertaining to the reliability of the gate dielectric.

By: D. A. Buchanan and S.-H. Lo

Published in: RC20778 in 1997


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